Self-Timed Power-Aware Pipeline Chip and Its Evaluation

This paper describes an experimental chip of self-timed (clockless) power-aware pipeline incorporating stage-by-stage power gating scheme. Its power gating circuit cuts the voltage-supply to the idle pipeline stages in order to reduce the static (leakage) power dissipation. To reduce the dynamic power dissipation, self-timed pipeline (STP) is one of the suitable circuit architectures because its ondemand transfer control activates only the pipeline stages operating valid data and thus unexpected signal propagation resulting in transistor switching is gated at pipeline stage level. Moreover, each pipeline stage can be slowed down in parallel with processing by introducing dynamic voltage scaling techniques and thus both the dynamic and static power dissipations can be reduced. In this paper, powerperformance characteristics of the self-timed power-aware pipeline (ULP-STP) are experimentally analyzed through measuring the actual 65nm CMOS LSI chips and simulating the optimized ULP-STP. The experimental results indicate that autonomous power-awareness of the ULP-STP can save about 48 % power in case of intermittent operation mode.